Reflex Ces FPGA Boards

reflex ces, your one-stop partner to build state-of-the-art embedded solutions.

State-of-the-arts electronics.

Reflex ces and apissys are advanced technology experts. Since 2000, we have collaborated with global market leaders to design and manufacture cutting-edge FPGA boards and systems.

Electronics is everywhere. It underlies every connection in a world where interactions are faster and increasingly complex. Defense, Bioscience, Instrumentation, Fintech, Networking: we specialize in high-value applications crucial to national security and competitiveness.

High Frequency Trading

REFLEX CES has been designing with the latest and leading-edge FPGA technologies for the Finance market for the last 10 years.

We understand the need for Ultra Low Latency for High Frequency Trading (HFT), and therefore work with several IP vendors to provide easy-to-use reference designs based on Ultra Low Latency MAC, Low Latency UDP/TCP - see our Partner section for more information. OpenCL is used for applications such as Risk analysis, and REFLEX CES offers HPC OpenCL BSPs as well as OpenCL BSPs targeting other interfaces such as 10G MAC or QDR support.

High Performance Computing

REFLEX CES designs with the latest leading-edge FPGA technologies which now compet with CPUs and GPUs in the High Performance Computing domain.

Our COTS boards, whether PCIe form factor or module types, are focused to provide the highest possible performance on the hardware side, together with the OpenCL BSP for ease-of-use on the software side. REFLEX CES can address server or chassis development based on customer specification, making the best feasibility study to solve power dissipation challenges.

IP & ASIC Prototyping

Due to increased circuit complexity, and time-to-market shrinking, the need for verification of application-specific-integrated-circuit (ASIC) and system-on-chip (SoC) designs is growing.

REFLEX CES Hardware platforms are more prominent due to the ability to test system designs at-speed with on-chip bus clocks, as compared to simulation clocks which may not provide an accurate reading of system behavior. In order to achieve optimal place and routing for partitioned designs, REFLEX CES focus on FPGA pin count and inter-FPGA signals.